This event was held on:

Tuesday, June 9, 2015
At the Design Automation Conference
San Francisco, CA

View the presentations from the workshop

Low power remains a hot topic for designers, verification engineers, IP developers and tool providers. In particular, interoperability among tools and IP remains a big concern for the engineers dealing with low power issues. In the past decade, standards have played an important role in building design and verification environment that address interoperability issues. Collectively, as the industry learns how to solve current issues, it uncovers that there are more issues to solve at system level in order to keep up with the growing complexity of designs and processes. Besides agreeing on the definition of system level, creation of power models and their suitability at different levels of abstraction for appropriate analysis remains a challenge.

With this in mind, a System Level Low Power workshop will be held at the 52nd Design Automation Conference (DAC). The workshop is co-organized and sponsored by the IEEE Design Automation Standards Committee (DASC), Si2 and Accellera Systems Initiative.

This workshop is free to all DAC attendees. Registration is required.

Agenda

1:15pm: Registration and networking

1:30pm: Welcome – John Ellis, Si2

1:45pm: System Level Power Modeling Usage and Requirements
Presentations from Users:

• Vita Vishnyakov, Microsoft
• Ahmad Ansari, Xilinx
• Barry Pangrle, Consultant
• Tom Quan, TSMC

3:15pm: System Level Power Standardization

• Stan Krolikoski , Chair, DASC LP Coordination Committee
• Sushma Honnavara-Prasad, Secretary, IEEE 1801
• Vojin Zivojnovich, Chair, IEEE 2415
• Nagu Dhanwada, Chair, IEEE 2416
• Jerry Frenkil, Director Low Power, Si2 Low Power Coalition

3:45pm: Facilitated Discussion – John Redmond, Broadcom

• Perceived Standards Gaps
• Perceived Standards Overlaps

4:25pm: Closing Remarks – Shishpal Rawat, Accellera

4:30pm: End of Workshop

This workshop is co-sponsored by: